The present invention relates to the field of electronic design automation and circuit timing analysis models. In particular, the present invention pertains to a method for modeling transparency in a black box timing model.
Integrated circuits can be represented as netlists within electronic design automation systems. A circuit timing analyzer takes a netlist of a circuit and the associated timing information for a circuit, and abstracts them to get a timing representation of the circuit. The timing model is then used by a circuit analyzer to predict the overall performance of the circuit, identify critical paths in the circuit, and find timing violations. A timing analysis estimates the signal propagation delays through a netlist. Prior art circuit analyzers are described by U.S. Pat. No. 5,740,347, entitled xe2x80x9cCircuit Analyzer of Black, Gray and Transparent Elements,xe2x80x9d by Jacob Avidan, issued Apr. 14, 1998, and by U.S. Pat. No. 5,790,830, entitled xe2x80x9cExtracting Accurate and Efficient Timing Models of Latch-Based Designs,xe2x80x9d by Russell B. Segal, issued Aug. 4, 1998, herein incorporated by reference in their entirety.
One common type of timing model known in the art is a black box model. A black box model uses setup and hold times between a data input pin and a clock, clock-to-output pin delays, input-to-output combinational delays, and other timing information to analyze the timing behavior of a circuit, typically in the context of surrounding circuits. Black box modeling has some advantages and so is widely used in prior art circuit analyzers. For example, black box modeling can reduce the size of timing models so that they require less memory in a computer system and can be processed faster. Reducing size and speeding up processing are desirable attributes, in particular for large and complex circuits, especially when these circuits are designed and analyzed at the transistor level.
Prior Art FIG. 1 exemplifies a latch 10 used in a black box model. Input data are provided to latch 10 via data input pin 30, and the output of latch 10 is via data output pin 40. A clock signal is connected to latch 10 via clock input pin 20. Some latches are active when the clock signal is at high voltage (xe2x80x9cactive highxe2x80x9d), and some latches are active when the clock signal is at low voltage (xe2x80x9cactive lowxe2x80x9d). For a clock that is active high, for example, when the clock signal transitions from high voltage to low voltage, the input data are latched and held until the clock transitions back to high again, when new data are latched.
Due to the physical characteristics of electronic circuitry, the input data must be available at data input pin 30 a certain amount of time before the clock signal transitions, in order for the input data to reach a stable state before it is latched. This time is referred to as setup time. Setup time is the difference between the clock delay Cl and the data delay D1; thus, setup time=D1xe2x88x92C1.
Setup time can be a function of either the leading edge or the trailing edge of the clock signal. In the former case, the data input must arrive at data input pin 30 before the clock signal transitions to its active state; in the latter case, latch 10 can sample data after the clock transitions to its active state.
A disadvantage to black box modeling is that in the modeling a latch is not permitted to sample data after the clock transitions to its active state (that is, after the leading edge of the clock signal), even though the circuit may actually sense data after that point in time. Thus, a disadvantage to black box modeling is that it does not support latch transparency. As a result, black box modeling can lead to overly restrictive constraints being placed on a circuit design, by requiring that data arrive at data input pin 30 before the clock signal transitions to its active state, when in fact it may be acceptable for the data to arrive afterwards. For instance, in some cases it might be possible for the input data to become stable in less than a clock cycle, and in those cases it would be acceptable for the data to arrive after the clock transitions to its active state. However, as already noted, black box modeling does not permit this to occur.
Conversely, black box modeling can introduce too strict timing constraints into the circuit analysis by predicting that the timing of a circuit is not satisfactory, when in reality the design of the circuit might be acceptable. For instance, the model might indicate that the data arrived at input pin 30 too late (e.g., after the clock has transitioned to its active state), although in reality the data might have arrived with enough time remaining in the clock cycle for the data to stabilize, as explained above.
In addition, when a circuit analyzer is applied at the transistor level of a circuit (that is, at the lowest level in the hierarchy of the timing analysis), a higher level of accuracy is desired for the circuit analysis. Therefore, a reduction in accuracy due to the prior art technique for black box modeling is particularly undesirable at the transistor level, and can lead to too strict timing constraints.
Accordingly, a need exists for a method to analyze the timing of a circuit without the unnecessarily restrictive constraints that can be placed on the circuit design when black box models are used. A need also exists for a method that accomplishes the above need and can be implemented at the transistor level. The present invention solves these needs. These and other objects and advantages of the present invention will become clear to those of ordinary skill in the art in light of the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
The present invention provides a method and system thereof that does not unnecessarily place restrictive constraints on a circuit design. The present invention also provides a method and system thereof for analyzing the timing of a circuit that can be implemented in circuit analyzers that use black box models. Furthermore, the present invention provides a method and system thereof that can be implemented at the transistor level.
The present invention pertains to a modeling method to incorporate transparency into black box models. A method is described for modeling transparency using setup time in a circuit timing model. By introducing transparency into a black box model, the timing constraints applied in the timing model can be relaxed.
In the present embodiment, input data are generated based on a netlist for a circuit comprising a plurality of latches. For each of the plurality of latches, an arrival time is calculated from the latch clock pin to an interface data output pin of the timing model, and the maximum arrival time is determined. A path search from the interface data input pin can be performed, and the latches on the path are found. For each of the latches, a setup time is calculated. A setup time is also calculated using the delay time from the interface data input pin to the interface data output pin and the maximum arrival time (that is, the interface data output pin is treated as a xe2x80x9cdummy latchxe2x80x9d). The worst-case setup time is selected from these setup times and imposed at the interface data input pin. Satisfaction of the worst-case setup time causes the maximum arrival time to also be satisfied. Therefore, a transparent path through the latches in the black box timing model cannot generate an arrival time at the interface data output pin greater than the maximum permissible arrival time.
In one embodiment, at least one of the plurality of latches represents the transistor level of the circuit.
In alternate embodiments, the present invention can be implemented in a timing model having a plurality of interface data input pins and/or a plurality of interface data output pins. A path search is performed to trace the various paths in the circuit.
The black box timing model generated in accordance with the present invention can be used with a plurality of other timing models in a hierarchical timing analysis that can include the transistor level.